`timescale 1ns / 1ns
// Digital IQ Interface
// Author: Michel Barbeau
// Version: Janurary 2, 2015
module DigitalInterface(clock, reset, I, Q, IQSel, IQ);

   input clock;
   input reset;   
   // I is the in-phase sample, Q is the quadrature sample
   input signed [11:0] I, Q; 
   // in-phase, quadrature selector
   output reg IQSel;
   // in-phase or quadrature output
   output reg [11:0] IQ; 
   // next state of IQSel
   reg IQSelState;
   
   initial 
      IQSelState <= 0;
   
   always @(posedge clock)
   begin
      if(reset)
         IQSelState <= 0; 
      else
        begin
         IQSel <= IQSelState;
         if (IQSel)
            // post an in-phase sample,
            // shifted in the 0..2^n-1 range
            IQ <= I[11] ? {1'b0,I[10:0]} : {1'b1,I[10:0]};
         else
            // post a quadrature sample,
            // shifted in the 0..2^n-1 range
            IQ <= Q[11] ? {1'b0,Q[10:0]} : {1'b1,Q[10:0]}; 
         IQSelState <= !	IQSelState;      
       end
   end
endmodule