Led by Prof. Yiqiang Q.
This research is aimed at developing and implementing high
performance packet classification algorithms in a fast packet
switching router. It is beneficial for developing new router
architectures, which are optimized for integrating new algorithms.
Nowadays, there are many alternatives for implementing the IP
lookup/packet classification in hardware. Typically, we have choices
of on-chip SRAM, on-chip DRAM, off-chip SRAM, off-chip DRAM or CAM.
The architecture can be pipelined or parallel. There are also
tradeoffs between memory bandwidth and logic design complexity. How
to achieve an optimal design among these parameters needs original
analysis and development.